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Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer AD5259
FEATURES
Nonvolatile memory maintains wiper settings 256-position Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package Compact MSOP-10 (3 mm x 4.9 mm x 1.1mm) package I2C(R)-compatible interface VLOGIC pin provides increased interface flexibility End-to-end resistance 5 k, 10 k, 50 k, 100 k Resistance tolerance stored in EEPROM (0.1% accuracy) Power-on EEPROM refresh time < 1ms Software write protect command Address Decode Pin AD0 and Pin AD1 allow 4 packages per bus 100-year typical data retention at 55C Wide operating temperature -40C to +85C 3 V to 5 V single supply
VDD VLOGIC GND 8 I2C SERIAL INTERFACE 8 DATA CONTROL COMMAND DECODE LOGIC ADDRESS DECODE LOGIC CONTROL LOGIC RDAC EEPROM RDAC REGISTER
FUNCTIONAL BLOCK DIAGRAMS
RDAC A W B
SCL SDA
AD0 AD1
AD5259
05026-001
POWERON RESET
Figure 1. Block Diagram
VLOGIC VDD A EEPROM
APPLICATIONS
LCD panel VCOM adjustment LCD panel brightness and contrast control Mechanical potentiometer replacement in new designs Programmable power supplies RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment Fiber to the home systems Electronics level settings
SCL SDA AD0 AD1
I2 C SERIAL INTERFACE COMMAND DECODE LOGIC ADDRESS DECODE LOGIC CONTROL LOGIC
RDAC REGISTER AND LEVEL SHIFTER W
GND
B
Figure 2. Block Diagram Showing Level Shifters
GENERAL DESCRIPTION
The AD5259 provides a compact, nonvolatile LFCSP-10 (3 mm x 3 mm) or MSOP-10 (3 mm x 4.9 mm) packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers 1 or variable resistors, but with enhanced resolution and solid-state reliability. The wiper settings are controllable through an I2C-compatible digital interface that is also used to read back the wiper register and EEPROM content. Resistor tolerance is also stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%. A separate VLOGIC pin delivers increased interface flexibility. For users who need multiple parts on one bus, Address Bit AD0 and Address Bit AD1 allow up to four devices on the same bus.
1
CONNECTION DIAGRAM
W1 AD0 2 AD1 3
10
A B
AD5259
9
SCL 5
6
VLOGIC
Figure 3. Pinout
The terms digital potentiometer, VR (variable resistor), and RDAC are used interchangeably.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05026-002
8 VDD TOP VIEW SDA 4 (Not to Scale) 7 GND
05026-003
AD5259 TABLE OF CONTENTS
Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Test Circuits..................................................................................... 13 Theory of Operation ...................................................................... 14 Programming the Variable Resistor......................................... 14 Programming the Potentiometer Divider ............................... 14 I2C-Compatible Interface............................................................... 15 Writing ......................................................................................... 15 Storing/Restoring ....................................................................... 15 Reading ........................................................................................ 15 I2C-Compatible Format ................................................................. 16 Generic Interface ........................................................................ 16 Write Modes................................................................................ 16 Read Modes................................................................................. 17 Store/Restore Modes .................................................................. 17 Tolerance Readback Modes ...................................................... 18 ESD Protection of Digital Pins and Resistor Terminals........ 19 Power-Up Sequence ................................................................... 19 Layout and Power Supply Bypassing ....................................... 19 Multiple Devices on One Bus ................................................... 19 Evaluation Board ........................................................................ 19 Display Applications ...................................................................... 20 Circuitry ...................................................................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
7/05 -- Rev. 0 to Rev. A Added 10-Lead LFCSP.......................................................Universal Changes to Features Section and General Description Section ........................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2 and Added Figure 4 ........................................ 5 Changes to Table 4............................................................................ 7 Changes to Figure 27 Caption....................................................... 11 Changes to Theory of Operation Section.................................... 14 Changes to I2C-Compatible Interface Section............................ 15 Changes to Table 5.......................................................................... 16 Changes to Multiple Devices on One Bus Section..................... 19 Updated Figure 49 Caption ........................................................... 21 Changes to Ordering Guide .......................................................... 21 2/05 -- Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5259 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = VLOGIC = 5 V 10% or 3 V 10%; VA = VDD; VB = 0 V; -40C < TA < +85C, unless otherwise noted.
B
Table 1.
Parameter DC CHARACTERISTICS: RHEOSTAT MODE Resistor Differential Nonlinearity 5 k 10 k 50 k/100 k Resistor Integral Nonlinearity 5 k 10 k 50 k/100 k Nominal Resistor Tolerance Resistance Temperature Coefficient Total Wiper Resistance DC CHARACTERISTICS: POTENTIOMETER DIVIDER MODE Differential Nonlinearity 5 k 10 k 50 k/100 k Integral Nonlinearity 5 k 10 k 50 k/100 k Full-Scale Error 5 k 10 k 50 k/100 k Zero-Scale Error 5 k 10 k 50 k/100 k Voltage Divider Temperature Coefficient RESISTOR TERMINALS Voltage Range Capacitance A, B Capacitance W Common-Mode Leakage Symbol Conditions Min Typ 1 Max Unit
R-DNL
RWB, VA = no connect -1 -1 -0.5 0.2 0.1 0.1 0.3 0.2 0.4 500/15 75 350 +1 +1 +0.5
LSB
R-INL
RWB, VA = no connect -4 -2 -1 -30 +4 +2 +1 +30
LSB
RAB (RAB x 106)/ (RAB x T) RWB
TA = 25C, VDD = 5.5 V Code = 0x00/0x80 Code = 0x00
% ppm/C
DNL -1 -0.5 -0.5 INL -1 -0.5 -0.5 VWFSE Code = 0xFF -7 -4 -1 VWZSE Code = 0x00 0 0 0 (VW x 106)/ (VW x T) VA, B, W CA, B CW ICM Code = 0x00/0x80 2.5 1 0.2 60/5 4 3 0.5 -3 -1.5 -0.4 0 0 0 0.2 0.1 0.1 +1 +0.5 +0.5 0.2 0.1 0.2 +1 +0.5 +0.5
LSB
LSB
LSB
LSB
ppm/C
GND f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VA = VB = VDD/2 45 60 10
VDD
V pF pF nA
Rev. A | Page 3 of 24
AD5259
Parameter DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Leakage Current SDA, AD0, AD1 SCL - Logic High SCL - Logic Low Input Capacitance POWER SUPPLIES Power Supply Range Positive Supply Current Logic Supply Logic Supply Current Programming Mode Current (EEPROM) Power Dissipation Power Supply Rejection Ratio DYNAMIC CHARACTERISTICS Bandwidth -3 dB Symbol VIH VIL IIL VIN = 0 V or 5 V VIN = 0 V VIN = 5 V CIL VDD IDD VLOGIC ILOGIC ILOGIC(PROG) PDISS PSRR BW 2.7 0.1 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V 10%, code = 0x80 Code = 0x80 RAB = 5 k RAB = 10 k RAB = 50 k RAB = 100 k RAB = 10 k, VA = 1 V rms, VB = 0, f = 1 kHz RAB = 10 k, VAB = 5 V, 1 LSB error band RWB = 5 k, f = 1 kHz
B
Conditions
Min 0.7 x VL -0.5
Typ 1
Max VL + 0.5 0.3 x VL
Unit V V A
-2.5
0.01 -1.3 0.01 5
1 +1 1 pF 5.5 2 5.5 6 40 0.06 V A V A mA W %/%
3 35 15 0.005
Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density
1
THDW tS eN_WB
2000 800 160 80 0.01 500 9
kHz kHz kHz kHz % ns nV/Hz
Typical values represent average readings at 25C and VDD = 5 V.
Rev. A | Page 4 of 24
AD5259
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V 10% or 3 V 10%; VA = VDD; VB = 0 V; -40C < TA < +85C, unless otherwise noted.
B
Table 2.
Parameter I2C INTERFACE TIMING CHARACTERISTICS 1 SCL Clock Frequency tBUF Bus Free Time Between Stop and Start tHD;STA Hold Time (Repeated Start) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Repeated Start Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for Stop Condition EEPROM Data Storing Time EEPROM Data Restoring Time at Power On 2 EEPROM Data Restoring Time upon Restore Command2 EEPROM Data Rewritable Time 3 FLASH/EE MEMORY RELIABILITY Endurance 4 Data Retention 5
1 2
Symbol
Conditions
Min
Typ
Max
Unit
fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 tEEMEM_STORE tEEMEM_RESTORE1 tEEMEM_RESTORE2 tEEMEM_REWRITE After this period, the first clock pulse is generated.
0 1.3 0.6 1.3 0.6 0.6 0 100
400
kHz s s s s s
0.9 300 300
s ns ns ns s ms s s s kCycles Years
0.6 VDD rise time dependent. Measure without decoupling capacitors at VDD and GND. VDD = 5 V. 26 300 300 540 100 700 100
Standard I2C mode operation guaranteed by design. During power-up, the output is momentarily preset to midscale before restoring EEPROM content. 3 Delay time after power-on PRESET prior to writing new EEPROM data. 4 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at -40C, +25C, and +85C; typical endurance at +25C is 700,000 cycles. 5 Retention lifetime equivalent at junction temperature (TJ) = 55C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature.
t8
SCL
t6
t9
t2
t2
t3 t8 t9
t4
t7
t5
t10
SDA
t1
P S S P
Figure 4. I2C Interface Timing Diagram
Rev. A | Page 5 of 24
05026-004
AD5259 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD, VLOGIC to GND VA, VB, VW to GND IMAX Pulsed 1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance 2 JA: MSOP-10
1
Value -0.3 V to +7 V GND - 0.3 V, VDD + 0.3 V 20 mA 5 mA 0 V to 7 V -40C to +85C 150C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
200C/W
Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 24
AD5259 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W1 AD0 2 AD1 3
10
A B
AD5259
9
SCL 5
6
VLOGIC
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 Mnemonic W ADO AD1 SDA SCL VLOGIC GND VDD B A Description W Terminal, GND VW VDD. Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up. Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up. Serial Data Input/Output. Serial Clock Input. Positive edge triggered. Logic Power Supply. Digital Ground. Positive Power Supply. B Terminal, GND VB VDD. A Terminal, GND VA VDD.
B
Rev. A | Page 7 of 24
05026-008
8 VDD TOP VIEW SDA 4 (Not to Scale) 7 GND
AD5259 TYPICAL PERFORMANCE CHARACTERISTICS
VDD = VLOGIC = 5.5 V, RAB = 10 k, TA = +25C; unless otherwise noted.
1.5 1.3 1.1
RHEOSTAT MODE INL (LSB) POTENTIOMETER MODE DNL (LSB)
0.25 0.20 2.7V 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 0 32 64 96 128 160 CODE (Decimal) 192 224 -40C +25C +85C
05026-012
0.9 0.7 0.5 0.3 0.1 -0.1 -0.3 5.5V -0.5 0 32 64 96 128 160 CODE (Decimal) 192 224
05026-015
256
256
Figure 6. R-INL vs. Code vs. Supply Voltage
0.5 0.4
Figure 9. DNL vs. Code vs. Temperature
0.25 0.20
POTENTIOMETER MODE INL (LSB)
2.7V
RHEOSTAT MODE DNL (LSB)
0.3 0.2 0.1 0 -0.1 -0.2 -0.3
05026-017
0.15 0.10 2.7V 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 0 32 64 96 128 160 CODE (Decimal) 192 224
05026-011
5.5V
5.5V
-0.4 -0.5 0 32 64 96 128 160 CODE (Decimal) 192 224
256
256
Figure 7. R-DNL vs. Code vs. Supply Voltage
0.25 0.20 0.15 0.10 TA = +85C 0.05 0 -0.05 -0.10 -0.15
05026-010
Figure 10. INL vs. Supply Voltages
0.25 0.20
POTENTIOMETER MODE DNL (LSB)
POTENTIOMETER MODE INL (LSB)
0.15 2.7V 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 0 32 64 96 128 160 CODE (Decimal) 192 224
05026-013
5.5V
-0.20 -0.25 0 32 64
TA = +25C
TA = -40C
96 128 160 CODE (Decimal)
192
224
256
256
Figure 8. INL vs. Code vs. Temperature
Figure 11. DNL vs. Code vs. Supply Voltage
Rev. A | Page 8 of 24
AD5259
0.5 0.4 0.3
RHEOSTAT MODE INL (LSB)
2.0 1.8 1.6 ZSE @ VDD = 2.7V 1.4
0.2 +25C
ZSE (LSB)
0.1 -40C 0 -0.1 -0.2 -0.3
1.2 1.0 ZSE @ VDD = 5.5V 0.8 0.6 0.4
05026-014
-0.4 -0.5 0 32 64 +85C 96 128 160 CODE (Decimal) 192 224
0.2 0 -40
256
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 12. R-INL vs. Code vs. Temperature
Figure 15. Zero-Scale Error vs. Temperature
0.5 0.4
1
RHEOSTAT MODE DNL (LSB)
TA = -40C 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 CODE (Decimal) 192 224
05026-016
TA = +85C
IDD, SUPPLY CURRENT (A)
0.3
VDD = 5.5V
TA = +25C
256
0.1 -40
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 13. R-DNL vs. Code vs. Temperature
Figure 16. Supply Current vs. Temperature
0
ILOGIC, LOGIC SUPPLY CURRENT (A)
6 5 4 VDD = 5.5V 3 2 1 VDD = 2.7V
05026-021
-0.5
-1.0
FSE (LSB)
-1.5
FSE @ VDD = 5.5V
-2.0 FSE @ VDD = 2.7V -2.5
05026-024
0 -1 -40
-3.0 -40
-20
0
20 40 TEMPERATURE (C)
60
80
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 14. Full-Scale Error vs. Temperature
Figure 17. Logic Supply Current vs. Temperature vs. VDD
Rev. A | Page 9 of 24
05026-020
05026-023
AD5259
400 100k 300
RHEOSTAT MODE TEMPCO (ppm/C)
120 100k Rt @ VDD = 5.5V
50k 200 100 0 -100 -200 -300 -400 -500 -600 0 32 64 96 128 160 CODE (Decimal) 192 224 5k
05026-019
TOTAL RESISTANCE (k)
10k
100
80 50k Rt @ VDD = 5.5V 60
40 10k Rt @ VDD = 5.5V 5k Rt @ VDD = 5.5V
05026-025
20
256
0 -40
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 18. Rheostat Mode Tempco (RAB x 106)/(RAB x T) vs. Code
0 -6 -12 -18
Figure 21. Total Resistance vs. Temperature
70
POTENTIOMETER MODE TEMPCO (ppm/C)
60 50 40 30 20 10 0 -10 -20
05026-018
80H 40H 20H 10H
GAIN (dB)
10k 100k
-24 -30 -36 -42 -48 -54 -60 1k
08H 04H 02H 01H
-30 -40 0
32
64
96 128 160 CODE (Decimal)
192
224
256
10k
100k FREQUENCY (Hz)
1M
10M
Figure 19. Potentiometer Mode Tempco (VW x 106)/(VW x T) vs. Code
0 -6
Figure 22. Gain vs. Frequency vs. Code, RAB = 5 k
350 300
80H 40H 20H 10H
-12
250
RWB @ 0x00
-18
200 150 100 RWB @ VDD = 5.5V
05026-022
GAIN (dB)
RWB @ VDD = 2.7V
-24 08H -30 -36 -42 01H -48 -54 -60 1k
05026-027
04H 02H
50 0 -40
-20
0
20 40 TEMPERATURE (C)
60
80
10k
100k FREQUENCY (Hz)
1M
10M
Figure 20. RWB vs. Temperature
Figure 23. Gain vs. Frequency vs. Code, RAB = 10 k
Rev. A | Page 10 of 24
05026-026
50k
5k
AD5259
0 -6 -12 -18 80H 40H 20H 10H 08H 04H 02H -42 -48
05026-028
10k
VDD = VLOGIC = 5V 1k
GAIN (dB)
-30 -36
ILOGIC (A)
-24
VDD = VLOGIC = 3V 100
01H
-54 -60 1k
10k 100k FREQUENCY (Hz)
1M
10 0 1 2 VIH (V) 3 4 5
Figure 24. Gain vs. Frequency vs. Code, RAB = 50 k
0 -6 -12 -18 80H 40H 20H 10H 08H 04H 02H 01H -48 -54 -60 1k
05026-029
Figure 27. Logic Supply Current vs. Input Voltage
80 CODE = MIDSCALE, VA = VLOGIC, VB = 0V PSRR @ VLOGIC = 5V DC 10% p-p AC 60
GAIN (dB)
-30 -36 -42
PSRR (dB)
-24
40
PSRR @ VLOGIC = 3V DC 10% p-p AC
20
05026-054
10k 100k FREQUENCY (Hz)
1M
0 100
1k
10k FREQUENCY (Hz)
100k
1M
Figure 25. Gain vs. Frequency vs. Code, RAB = 100 k
Figure 28. PSRR vs. Frequency
0 -6 100k 80kHz 50k 160kHz 10k 800kHz 5k 2MHz
-18
200mV/DIV
-12
GAIN (dB)
-24 -30 -36 -42
VW
1
5V/DIV
-48 -54 -60 1k
05026-050
SCL
2
10k
100k FREQUENCY (Hz)
1M
10M
400ns/DIV
Figure 26. -3 dB Bandwidth @ Code = 0x80
Figure 29. Digital Feedthrough
Rev. A | Page 11 of 24
05026-051
05026-055
AD5259
50mV/DIV
VW
1
2V/DIV
VW
1
5V/DIV
SCL
05026-053
05026-052
2
1s/DIV
200ns/DIV
Figure 30. Midscale Glitch, Code 0x7F to 0x80
Figure 31. Large Signal Settling Time
Rev. A | Page 12 of 24
AD5259 TEST CIRCUITS
Figure 32 through Figure 37 illustrate the test circuits that define the test conditions used in the product Specifications tables.
VA
DUT A V+ B W V+ = VDD 1LSB = V+/2N
DUT VDD A V+ B W
V+ = VDD 10% VMS PSRR (dB) = 20 LOG V DD VMS% PSS (%/%) = VDD%
(
)
05026-033
Figure 32. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
05026-030
VMS
VMS
Figure 35. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
NO CONNECT DUT AW B
05026-031
DUT
IW
A VIN B
+5V
W AD8610 VOUT
05026-034
05026-035
VMS
OFFSET GND +2.5V
-5V
Figure 33. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure 36. Test Circuit for Gain vs. Frequency
DUT
RSW = 0.1V ISW W ISW CODE = 0x00 0.1V
DUT A VMS2 B W VW
IW = VDD/RNOMINAL
RW = [VMS1 - VMS2]/IW
05026-032
B GND TO VDD
VMS1
Figure 34. Test Circuit for Wiper Resistance
Figure 37. Test Circuit for Common-Mode Leakage Current
Rev. A | Page 13 of 24
AD5259 THEORY OF OPERATION
The AD5259 is a 256-position digitally-controlled variable resistor (VR) device. EEPROM is pre-loaded at midscale from the factory, and initial power-up is, accordingly, at midscale.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (RAB) of the RDAC between Terminal A and Terminal B is available in 5 k, 10 k, 50 k, and 100 k. The nominal resistance of the VR has 256 contact points accessed by the wiper terminal. The 8-bit data in the RDAC latch is decoded to select one of 256 possible settings.
A W A W A W
05026-036
Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A produces a digitally controlled complementary resistance, RWA. The resistance value setting for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is
RWA (D) =
256 - D x RAB + 2 x RW 256
(2)
Typical device-to-device matching is process lot dependent and may vary by up to 30%. For this reason, resistance tolerance is stored in the EEPROM, enabling the user to know the actual RAB within 0.1%.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at Wiper W to Terminal B and Wiper W to Terminal A proportional to the input voltage at Terminal A to Terminal B. Unlike the polarity of VDD to GND, which must be positive, voltage across Terminal A to Terminal B, Wiper W to Terminal A, and Wiper W to Terminal B can be at either polarity.
VI A W VO
05026-038
B
B
B
Figure 38. Rheostat Mode Configuration
The general equation determining the digitally programmed output resistance between Wiper W and Terminal B is
RWB (D) =
D x RAB + 2 x RW 256
(1)
where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the ON resistance of each internal switch.
A RS
B
Figure 40. Potentiometer Mode Configuration
D7 D6 D5 D4 D3 D2 D1 D0
RS
RS W
If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at Wiper W to Terminal B starting at 0 V up to 1 LSB less than 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is
VW (D) = D 256 - D VA + VB 256 256
(3)
A more accurate calculation, which includes the effect of wiper resistance, VW, is
RDAC LATCH AND DECODER RS B
05026-037
VW (D ) =
R (D ) RWB (D ) VA + WA VB RAB RAB
(4)
Figure 39. AD5259 Equivalent RDAC Circuit
In the zero-scale condition, there is a relatively low value finite wiper resistance. Care should be taken to limit the current flow between Wiper W and Terminal B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or destruction of the internal switch contact can occur.
Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the Internal Resistors RWA and RWB and not the absolute values.
Rev. A | Page 14 of 24
AD5259 I2C-COMPATIBLE INTERFACE
The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 4). The next byte is the slave address byte, which consists of the slave address (first 7 bits) followed by an R/W bit (see Table 6). When the R/W bit is high, the master reads from the slave device. When the R/W bit is low, the master writes to the slave device. The slave address of the part is determined by two configurable address pins, Pin AD0 and Pin AD1. The state of these two pins is registered upon power-up and decoded into a corresponding I2C 7-bit address (see Table 5). The slave address corresponding to the transmitted address bits responds by pulling the SDA line low during the ninth clock pulse (this is termed the slave acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register.
READING
Assuming the register of interest was not just written to, it is necessary to write a dummy address and instruction byte. The instruction byte will vary depending on whether the data that is wanted is the RDAC register, EEPROM register, or tolerance register (see Table 11 and Table 16). After the dummy address and instruction bytes are sent, a repeat start is necessary. After the repeat start, another address byte is needed, except this time the R/W bit is logic high. Following this address byte is the readback byte containing the information requested in the instruction byte. Read bits appear on the negative edges of the clock. The tolerance register can be read back individually (see Table 15) or consecutively (see Table 16). Refer to the Read Modes section for detailed information on the interpretation of the tolerance bytes. After all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-tohigh transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 46). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, and then raises SDA high to establish a stop condition (see Figure 47). A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in the write mode, the RDAC output is updated on each successive byte until a stop condition is received. If different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed.
WRITING
In the write mode, the last bit (R/W) of the slave address byte is logic low. The second byte is the instruction byte. The first three bits of the instruction byte are the command bits (see Table 6). The user must choose whether to write to the RDAC register, EEPROM register, or activate the software write protect (see Table 7 to Table 10). The final five bits are all zeros (see Table 13 to Table 14). The slave again responds by pulling the SDA line low during the ninth clock pulse. The final byte is the data byte MSB first. With the write protect mode, data is not stored; rather, a logic high in the LSB enables write protect. Likewise, a logic low disables write protect. The slave again responds by pulling the SDA line low during the ninth clock pulse.
STORING/RESTORING
In this mode, only the address and instruction bytes are necessary. The last bit (R/W) of the address byte is logic low. The first three bits of the instruction byte are the command bits (see Table 6). The two choices are transfer data from RDAC to EEPROM (store), or from EEPROM to RDAC (restore). The final five bits are all zeros (see Table 13 to Table 14).
Rev. A | Page 15 of 24
AD5259 I2C-COMPATIBLE FORMAT
The following generic, write, read, and store/restore control registers for the AD5259 all refer to the device addresses listed in Table 5; the mode/condition reference key (S, P, SA, MA, NA, W, R, and X) is listed below.
S = Start Condition P = Stop Condition SA = Slave Acknowledge MA = Master Acknowledge NA = No Acknowledge W = Write R = Read X = Don't Care
AD1 and AD0 are two-state address pins.
Table 5. Device Address Lookup
AD1 Address Pin 0 1 0 1 AD0 Address Pin 0 0 1 1
I2C Device Address
0011000 0011010 1001100 1001110
GENERIC INTERFACE
Table 6. Generic Interface Format
S 7-Bit Device Address (See Table 5) Slave Address Byte R/W SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P Instruction Byte Data Byte
Table 7. RDAC-to-EEPROM Interface Command Descriptions
C2 0 0 0 1 1 1 C1 0 0 1 0 0 1 C0 0 1 0 0 1 0 Command Description Operation Between Interface and RDAC. Operation Between Interface and EEPROM. Operation Between Interface and Write Protection Register. See Table 10. NOP. Restore EEPROM to RDAC. Store RDAC to EEPROM.
WRITE MODES
Table 8. Writing to RDAC Register
7-Bit Device Address S (See Table 5) Slave Address Byte 0 SA 0 0 0 0 Instruction Byte 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P Data Byte
Table 9. Writing to EEPROM Register
7-Bit Device Address S (See Table 5) Slave Address Byte 0 SA 0 0 1 0 Instruction Byte 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P Data Byte
Table 10. Activating/Deactivating Software Write Protect
S 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 0 1 0 0 Instruction Byte 0 0 0 0 SA 0 0 0 Data Byte 0 0 0 0 WP SA P
In order to activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the command must be sent again, except with the WP in logic zero state. WP is reset to the deactivated mode if power is cycled off and on.
Rev. A | Page 16 of 24
AD5259
READ MODES
Read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes, which function to place the pointer towards the correct register; this is the reason for the repeat start. Theoretically, this step can be avoided if the user reads a register previously written to. For example, if the EEPROM was just written to, the user can then skip the two dummy bytes and proceed directly to the slave address byte, followed by the EEPROM readback data.
Table 11. Traditional Readback of RDAC Register Value
S 7-Bit Device Address (See Table 5) Slave Address Byte
0 SA 0 0 0 0 0 0 0 0 SA S
Instruction Byte
7-Bit Device Address (See Table 5) Slave Address Byte
1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Read Back Data
Repeat start
Table 12. Traditional Readback of Stored EEPROM Value
7-Bit Device Address S (See Table 5) Slave Address Byte 7-Bit Device Address
0 SA 0 0 1 0 0 0 0 0 SA S (See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Instruction Byte
Slave Address Byte Repeat start
Read Back Data
STORE/RESTORE MODES
Table 13. Storing RDAC Value to EEPROM
S 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 1 1 0 Instruction Byte 0 0 0 0 0 SA P
Table 14. Restoring EEPROM to RDAC
S 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 1 0 1 Instruction Byte 0 0 0 0 0 SA P
Rev. A | Page 17 of 24
AD5259
TOLERANCE READBACK MODES
Table 15. Traditional Readback of Tolerance (Individually)
7-Bit Device Address S (See Table 5) Slave Address Byte 7-Bit Device Address 0 SA 0 0 1 1 1 1 1 0 SA S (See Table 5) Instruction Byte Slave Address Byte Repeat start 7-Bit Device Address 0 SA 0 0 1 1 1 1 1 1 SA S (See Table 5) Instruction Byte Slave Address Byte Repeat start 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P Sign + Integer Byte
7-Bit Device Address S (See Table 5) Slave Address Byte
1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P Decimal Byte
Table 16.Traditional Readback of Tolerance (Consecutively)
7-Bit Device Address S (See Table 5) Slave Address Byte 7-Bit Device Address 0 SA 0 0 1 1 1 1 1 0 SA S (See Table 5) Slave Address Instruction Byte Byte Repeat start
1 SA D7 D6 D5 D4 D3 D2 D1 D0 MA D7 D6 D5 D4 D3 D2 D1 D0 NA P Sign + Integer Byte Decimal Byte
Calculating RAB Tolerance Stored in Read-Only Memory
A D7 SIGN D6 26 D5 25 D4 24 D3 23 D2 22 D1 21 D0 20 A D7 2-1 D6 2-2 D5 2-3 D4 2-4 D3 2-5 D2 2-6 D1 2-7 D0 2-8
05026-005
A
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 41. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is Percent. Only Data Bytes are Shown.)
The AD5259 features a patented RAB tolerance storage in the nonvolatile memory. The tolerance is stored in the memory during factory production and can be read by users at any time. The knowledge of stored tolerance allows users to accurately calculate RAB. This feature is valuable for precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical. The stored tolerance resides in the read-only memory and is expressed as a percentage. The tolerance is stored in two memory location bytes in sign magnitude binary form (see Figure 41). The two EEPROM address bytes are 11110 (sign + integer) and 11111 (decimal number). The two bytes can be individually accessed with two separate commands (see Table 15). Alternatively, readback of the first byte followed by the second byte can be done in one command (see Table 16). In the latter case, the memory pointer will automatically increment from the first to the second EEPROM location (increments from 11110 to 11111) if read consecutively.
In the first memory location, the MSB is designated for the sign (0 = + and 1= -) and the seven LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. Note the decimal portion has a limited accuracy of only 0.1%. For example, if the rated RAB = 10 k and the data readback from Address 11110 shows 0001 1100, and Address 11111 shows 0000 1111, then the tolerance can be calculated as MSB: 0 = + Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 x 2-8 = 0.06 Tolerance = +28.06% Rounded Tolerance = +28.1% and therefore, RAB_ACTUAL = 12.810 k
Rev. A | Page 18 of 24
AD5259
ESD PROTECTION OF DIGITAL PINS AND RESISTOR TERMINALS
The AD5259 VDD, VLOGIC, and GND power supplies define the boundary conditions for proper 3-terminal and digital input operation. Supply signals present on Terminal A, Terminal B, and Terminal W that exceed VDD or GND are clamped by the internal forward biased ESD protection diodes (see Figure 42). Digital Input SCL and Digital Input SDA are clamped by ESD protection diodes with respect to VLOGIC and GND as shown in Figure 43.
VDD
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to use compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 44). The digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.
VDD C2 10F VDD C1 0.1F
A W B
05026-039
GND
+
Figure 42. Maximum Terminal Voltages Set by VDD and GND
VLOGIC
AD5259
GND
05026-041
SCL SDA
Figure 44. Power Supply Bypassing
05026-040
GND
MULTIPLE DEVICES ON ONE BUS
The AD5259 has two configurable address pins, Pin AD0 and Pin AD1. The state of these two pins is registered upon powerup and decoded into a corresponding I2C-compatible 7-bit address (see Table 5). This allows up to four devices on the bus to be written to or read from independently.
Figure 43. Maximum Terminal Voltages Set by VLOGIC and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 42), it is important to power GND/VDD/VLOGIC before applying any voltage to Terminal A, Terminal B, and Terminal W; otherwise, the diode is forward biased, so the VDD and VLOGIC are powered unintentionally and may affect the user's circuit. The ideal powerup sequence is in the following order: GND, VDD, VLOGIC, digital inputs, and then VA, VB, VW. The relative order of powering VA, VBB, VW, and the digital inputs is not important as long as they are powered after GND/VDD/VLOGIC.
B
EVALUATION BOARD
An evaluation board, with all necessary software, is available to program the AD5259 from any PC running Windows(R) 98/ 2000/ XP. The graphical user interface, as shown in Figure 45, is straightforward and easy to use. More detailed information is available in the board's user manual.
Figure 45. AD5259 Evaluation Board Software
Rev. A | Page 19 of 24
05026-042
AD5259 DISPLAY APPLICATIONS
CIRCUITRY
A special feature of the AD5259 is its unique separation of the VLOGIC and VDD supply pins. The separation provides greater flexibility in applications that do not always provide needed supply voltages. In particular, LCD panels often require a VCOM voltage in the range of 3 V to 5 V. The circuit in Figure 46 is the rare exception in which a 5 V supply is available to power the digital potentiometer.
VCC (~3.3V) 5V 14.4V R1 70k C1 1F R6 10k R5 10k
For this reason, VLOGIC and VDD are provided as two separate supply pins that can either be tied together or treated independently; VLOGIC supplying the logic/EEPROM with power, and VDD biasing up the A, B, and W terminals for added flexibility.
VCC (~3.3V) SUPPLIES POWER 14.4V TO BOTH THE R1 MICRO AND THE 70k LOGIC SUPPLY OF THE DIGITAL POT C1 AD5259 1F R6 R5 VDD 10k 10k VLOGIC R2 A 10k SCL MCU W SDA B GND
-
U1 AD8565
+ 3.5V < VCOM < 4.5V
AD5259
VDD VLOGIC SCL SDA GND R3 25k R2 A 10k
B W
-
MCU
+
3.5V < VCOM < 4.5V
Figure 47. Circuitry When a Separate Supply is Not Available for VDD
For a more detailed look at this application, refer to the article, "Simple VCOM Adjustment uses any Logic Supply Voltage" in the September 30, 2004 issue of EDN magazine.
Figure 46. VCOM Adjustment Application
In the more common case shown in Figure 47, only analog 14.4 V and digital logic 3.3 V supplies are available. By placing discrete resistors above and below the digital potentiometer, VDD can now be tapped off the resistor string itself. Based on the chosen resistor values, the voltage at VDD in this case equals 4.8 V, allowing the wiper to be safely operated all the way up to 4.8 V. The current draw of VDD will not affect that node's bias because it is only on the order of microamps. VLOGIC is tied to the MCU's 3.3 V digital supply because VLOGIC will draw the 35 mA which is needed when writing to the EEPROM. It would be impractical to try and source 35 mA through the 70 k resistor, therefore, VLOGIC is not connected to the same node as VDD.
Rev. A | Page 20 of 24
05026-006
05026-007
U1 AD8565
R3 25k
AD5259 OUTLINE DIMENSIONS
3.00 BSC
INDEX AREA
3.00 BSC SQ
10
PIN 1 INDICATOR
1
10
6
3.00 BSC
1 5
4.90 BSC
1.50 BCS SQ
TOP VIEW
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
2.48 2.38 2.23
5
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40
0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM 0.20 REF
6
0.80 MAX 0.55 TYP
SIDE VIEW
1.74 1.64 1.49
SEATING PLANE
0.23 0.08
0.30 0.23 0.18
Figure 48. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5259BRMZ5 AD5259BRMZ5-R71 AD5259BCPZ5-R71 AD5259BRMZ101 AD5259BRMZ10-R71 AD5259BCPZ10-R71 AD5259BRMZ501 AD5259BRMZ50-R71 AD5259BCPZ50-R71 AD5259BRMZ1001 AD5259BRMZ100-R71 AD5259BCPZ100-R71 AD5259EVAL 2
1 2
RAB ()
1
5k 5k 5k 10 k 10 k 10 k 50 k 50 k 50 k 100 k 100 k 100 k
Temperature -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD Evaluation Board
Package Option RM-10 RM-10 CP-10-9 RM-10 RM-10 CP-10-9 RM-10 RM-10 CP-10-9 RM-10 RM-10 CP-10-9
Branding D4P D4P D4P D4Q D4Q D4Q D4R D4R D4R D4S D4S D4S
Z = Pb-free part. The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. A | Page 21 of 24
AD5259
NOTES
Rev. A | Page 22 of 24
AD5259
NOTES
Rev. A | Page 23 of 24
AD5259
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. D05026-0-7/05(A)
Rev. A | Page 24 of 24

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